The present invention relates to an electronic device and to a technology which is effective when applied to an electronic device in which, e.g., a plurality of semiconductor devices each including a semiconductor chip are mounted.
In Japanese Unexamined Patent Publication No. 2008-60256 (Patent Document 1), the technique shown below is described. That is, a first chip is mounted on a first die pad and a second chip is mounted on a second die pad. The first die pad and the second die pad are configured to be separated along a direction parallel with a first side and a second side of a sealing body. This allows output pins extending from the first chip and the control pins of a drive circuit to protrude in opposite directions.
In Japanese Unexamined Patent Publication No. 2008-21796 (Patent Document 2), a semiconductor device is described in which a semiconductor chip formed with an Insulated Gate Bipolar Transistor (hereinafter referred to as an IGBT in the present specification) and a semiconductor chip formed with a diode are mounted on a die pad.
In Japanese Unexamined Patent Publication No. 2011-86889 (Patent Document 3), a technique is described which mounts a plurality of single-body packages together on a metal substrate via an insulating adhesive sheet to form one composite package.
In Japanese Unexamined Patent Publication No. 2009-158787 (Patent Document 4), a technique is described which mounts, on a wiring board, a semiconductor chip formed with an IGBT and a semiconductor chip formed with a diode, each in a bare-chip state.